Solid-state storage devices such as solid-state disks (SSDs) have been increasingly employed in battery based systems such as laptop and tablet computers, as well as computerized devices such as smartphones. In a typical computer system or computerized device, a host computer can access an SSD via a computer bus interface. For example, the computer bus may be a serial advanced technology attachment (SATA) bus. The term “SATA” refers to a computer bus interface for connecting host bus adapters to mass storage devices such as SSDs, hard disk drives, and optical drives. A SATA controller or host adapter in a host computer can employ an advanced host controller interface (AHCI) to control a SATA bus between the host computer and an SSD. The term “AHCI” refers to a technical standard defined by Intel Corporation, Santa Clara, Calif., United States, that specifies the operation of SATA host bus adapters in a non-implementation-specific manner. SSDs may include non-volatile semiconductor storage media such as NAND or NOR flash memory for storing digital information (e.g., data, computer-executable instructions, applications) in arrays of memory cells. Because the digital information is stored in the NAND or NOR flash memory of an SSD, it can persist in the computer system or computerized device even if power is lost to the SSD. After power is restored to the SSD, the host computer can use the SATA controller to access the digital information from the SSD.
Due in no small part to the widespread use of SSDs in laptop/tablet computers as well as smartphones, techniques for reducing power consumption in SSDs have gained increased attention in recent years. For example, a SATA controller may be used to implement a power management technique that allows an SSD to be placed in a reduced power state, such as the known “Partial” or “Slumber” reduced power state. When placed in the Partial reduced power state, the SSD enters a reduced power mode (e.g., typically 200-850 milliwatts), and the resume latency is typically 6-10 μseconds. When placed in the Slumber reduced power state, the SSD enters a further reduced power mode (e.g., typically 100-200 milliwatts), however the resume latency is increased to typically 1.5-10 milliseconds. For both the Partial and Slumber reduced power states, the SATA controller and the SSD generally employ in-band signaling to transmit/receive commands required to change the respective power states, prohibiting the physical layer (PHY) interface of the SSD (also referred to herein as the “device PHY interface”) from being fully powered down.
To achieve even further reduced power consumption in SSDs, a SATA controller can be used to implement a power management technique that employs out-of-band signaling to transmit a control signal, such as the known “DEVSLP” signal, to an SSD. When the SATA controller asserts the DEVSLP signal, the SSD can enter the known “DevSleep” reduced power state. When the SATA controller negates the DEVSLP signal, the SSD can resume normal operation. Because out-of-band signaling is used to place the SSD in the DevSleep reduced power state, the device PHY interface can be fully powered down, thereby providing reduced power mode operation (e.g., typically about 5 milliwatts or less) with a resume latency of typically about 100 milliseconds or less.